1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly to a PMOS transistor and a method of manufacturing the same with increased effective length of a channel in a peripheral region of the PMOS transistor.
2. Description of the Prior Art
As the semiconductor devices are reduced at a level less than 100 nm, the important issues are to securing a margin of a threshold voltage Vt of a peripheral region of a PMOS transistor and reducing the leakage of the off current.
Unlike a CMOS transistor which must implement both NMOS and PMOS devices in a peripheral region, a PMOS transistor device is realized by a buried channel, which is advantageous in that the carriers have high mobility allowing a large operational current in the buried channel rather than near the surface of the transistor. However, shorter the length of the channel, the characteristics of the off current leakage become worse.
Further, electrons created by the holes that are carriers of the PMOS transistor are implanted in a gate oxide layer or an isolation layer. Even when a gate is turned off, such implanted electrons cause the channel of the PMOS transistor to be inverted, and this reduces the effective length of the channel. This phenomenon is referred to as a hot electron induced punch-through (HEIP). The HEIP increases the existing off current, which increases the consumption of electricity of the transistor.
Also, there is a problem in that the HEIP affects the operational speed and the other electric characteristics such as the decrease and deterioration of punch-through voltage of the PMOS transistor.
FIG. 1A is a plan view for illustrating a HEIP occurring in a PMOS transistor according to a conventional art, FIGS. 1B and 1C are cross-sectional views for taken along the lines I-I′ and II-II′ in FIG. 1A.
As shown in FIGS. 1A to 1C, the HEIP is the phenomenon that decrease the effective length of the channel by inverting the channel of the PMOS transistor by electrons caused at the both edge of lengthwise direction and widthwise direction of the channel.
Attempting to solve these problems, various conventional plans have been proposed. As shown in FIG. 2, One conventional plan proposes installation of a gate tap 6 in a region in which a reduction of the channel has arisen, but not in a whole gate line 3, thereby preventing a reduction of the effective length of the channel.
In FIGS. 1A to 1C and 2, a reference numeral “1” denotes a semiconductor substrate, a reference numeral “2” indicates a isolation layer, a reference numeral “3a” denotes a gate oxide layer, a reference numeral “3b” denotes a gate conductive layer, a reference numeral “3c” denotes a hard mask layer, a reference numeral “4” indicates a spacer, a reference numeral “5a” indicates a source region, and a reference numeral “5b” indicates a drain region.
However, with respect to the design rule for integration of the semiconductor devices reduced at a level less than 80 nm, it is difficult to secure a space in which a gate tap is to be installed. Hence, there is a limitation to overcome a deterioration of electric characteristics of the PMOS device.